____  _____  _____  _____  _____     __
|  _ \|  __ \|_   _|/ ____|/ ____|   /_ |
| |_) | |__) | | | | (___ | |   ______| |
|  _ <|  _  /  | |  \___ \| |  |______| |
| |_) | | \ \ _| |_ ____) | |____     | |
|____/|_|  \_\_____|_____/ \_____|    |_|

BRISC/1 - Basement Reduced Instruction Set Computer

Today's RISC processors are so far from RISC roots that they are no longer truly RISC.

The basement architecture demonstrates a minimalistic approach to developing a functional,
32 bit highly RISC processor, great for tinkering and experimenting.

The BRISC/1 CPU is constructed from discreet TTL logic.

OVERALL SPECS
-------------

* Target 8 MHz OSC signal (4 MHz CPU bus clock)
* 4 CLK cycles per instruction cycle.
* 2 T states (internal bus transfers) per instruction cycle.
  * T1 Execute Instruction.
  * T2 Fetch new instruction.
* 32 bit internal address bus.
* 32 bit internal data bus.
* Processor WAIT state support for slower peripherals.
* *FAULT state support for demand paging.
* 6 External Priority Scheduled Interrupts.
* Built on S100 card format
  * Execution Unit / Sequencer / ALU (i.e. CPU)
    * Clock chain.
    * Bus control logic.
    * Sequencer logic.
    * Microcode store.
    * ALU
      * 3 logic and 3 arithmetic operations
      * C,Z,S,P, and G Flags
      * 32 bit barrel shifter.
    * 32, 16, or 8 bit operands.


REGISTER ADDRESSES
------------------

0000 R0		GENERAL PURPOSE
0001 R1		GENERAL PURPOSE
0010 R2		GENERAL PURPOSE
0011 R3		GENERAL PURPOSE
0100 R4		GENERAL PURPOSE
0101 R5		GENERAL PURPOSE
0110 R6		GENERAL PURPOSE
0111 R7		GENERAL PURPOSE

1000 R8		GENERAL PURPOSE
1001 R9		GENERAL PURPOSE
1010 R10	GENERAL PURPOSE
1011 R11	GENERAL PURPOSE
1100 R12 (SP)	GENERAL PURPOSE/STACK POINTER
1101 R13 (LR)	LINK REGISTER
1110 R14 (PC)	PROGRAM COUNTER
1111 R15 (PSW)	PROGRAM STATUS WORD

INSTRUCTION TYPE 0
-------------------

MSB                          LSB
10987654321098765432109876543210
||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||+- 
||||||||||||||||||||||||||||||+-- 
|||||||||||||||||||||||||||||+--- CONDITION0
||||||||||||||||||||||||||||+---- CONDITION1
|||||||||||||||||||||||||||+----- CONDITION2
||||||||||||||||||||||||||+------ SHIFT0
|||||||||||||||||||||||||+------- SHIFT1
||||||||||||||||||||||||+-------- SHIFT2
|||||||||||||||||||||||+--------- SHIFT3
||||||||||||||||||||||+---------- SHIFT4
|||||||||||||||||||||+----------- INb ROTATE WITH CARRY
||||||||||||||||||||+------------ INb ROTATE
|||||||||||||||||||+------------- INb ~RIGHT/LEFT
||||||||||||||||||+-------------- INb ~LOGIC/ARITH SHIFT
|||||||||||||||||+--------------- INb REGISTER ADDRESS (BIT 0)
||||||||||||||||+---------------- INb REGISTER ADDRESS (BIT 1)
|||||||||||||||+----------------- INb REGISTER ADDRESS (BIT 2)
||||||||||||||+------------------ INb REGISTER ADDRESS (BIT 3)
|||||||||||||+------------------- INa REGISTER ADDRESS (BIT 0)
||||||||||||+-------------------- INa REGISTER ADDRESS (BIT 1)
|||||||||||+--------------------- INa REGISTER ADDRESS (BIT 2)
||||||||||+---------------------- INa REGISTER ADDRESS (BIT 3)
|||||||||+----------------------- OUT REGISTER ADDRESS (BIT 0)
||||||||+------------------------ OUT REGISTER ADDRESS (BIT 1)
|||||||+------------------------- OUT REGISTER ADDRESS (BIT 2)
||||||+-------------------------- OUT REGISTER ADDRESS (BIT 3)
|||||+--------------------------- ALU SET CONDITION FLAGS
||||+---------------------------- ALU S0
|||+----------------------------- ALU S1
||+------------------------------ ALU S2
|+------------------------------- ALU CY (1=APPLY CARRY FLAG  0=NO CARRY)
+-------------------------------- TYPE BIT (0)





INSTRUCTION TYPE 1 (MEMORY LOAD/STORE)
-------------------

MSB                          LSB
10987654321098765432109876543210
||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||+- IMMEDIATE DATA BIT 0
||||||||||||||||||||||||||||||+-- IMMEDIATE DATA BIT 1
|||||||||||||||||||||||||||||+--- IMMEDIATE DATA BIT 2
||||||||||||||||||||||||||||+---- IMMEDIATE DATA BIT 3
|||||||||||||||||||||||||||+----- IMMEDIATE DATA BIT 4
||||||||||||||||||||||||||+------ IMMEDIATE DATA BIT 5
|||||||||||||||||||||||||+------- IMMEDIATE DATA BIT 6
||||||||||||||||||||||||+-------- IMMEDIATE DATA BIT 7
|||||||||||||||||||||||+--------- IMMEDIATE DATA BIT 8
||||||||||||||||||||||+---------- IMMEDIATE DATA BIT 9
|||||||||||||||||||||+----------- IMMEDIATE DATA BIT 10
||||||||||||||||||||+------------ IMMEDIATE DATA BIT 11
|||||||||||||||||||+------------- IMMEDIATE DATA BIT 12
||||||||||||||||||+-------------- IMMEDIATE DATA BIT 13
|||||||||||||||||+--------------- IMMEDIATE DATA BIT 14
||||||||||||||||+---------------- IMMEDIATE DATA BIT 15
|||||||||||||||+----------------- CONDITIONAL BIT 0
||||||||||||||+------------------ CONDITIONAL BIT 1
|||||||||||||+------------------- CONDITIONAL BIT 2
||||||||||||+-------------------- INa/OUT REGISTER ADDRESS (BIT 0)
|||||||||||+--------------------- INa/OUT REGISTER ADDRESS (BIT 1)
||||||||||+---------------------- INa/OUT REGISTER ADDRESS (BIT 2)
|||||||||+----------------------- INa/OUT REGISTER ADDRESS (BIT 4)
||||||||+------------------------ ALU CONDITION FLAGS PROTECT
|||||||+------------------------- ALU S0
||||||+-------------------------- ALU S1
|||||+--------------------------- ALU S2
||||+---------------------------- ALU S3
|||+----------------------------- ALU M
||+------------------------------ ALU CARRY STATE (1=CARRY 0=NO CARRY)
|+------------------------------- ALU FORCE CARRY (1=FORCE CARRY 0=USE CARRY FLAG)
+-------------------------------- TYPE BIT (0)


ALU INSTRUCTION WORD
--------------------

3210
||||
|||+- S0
||+-- S1
|+--- S2
+---- CARRY


ALU STATUS WORD
---------------

10987654321098765432109876543210
||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||+- Z     # Zero
||||||||||||||||||||||||||||||+-- S     # Sign
|||||||||||||||||||||||||||||+--- C     # Carry
||||||||||||||||||||||||||||+---- P     # 74F181 P Flag
|||||||||||||||||||||||||||+----- G     # 74F181 G Flag
||||||||||||||||||||||||||+------ 0     ---
|||||||||||||||||||||||||+------- 0     ---
||||||||||||||||||||||||+-------- 0     ---
|||||||||||||||||||||||+--------- VID0  # Vectored Interrupt 0
||||||||||||||||||||||+---------- VID1  # Vectored Interrupt 1
|||||||||||||||||||||+----------- VID2  # Vectored Interrupt 2
||||||||||||||||||||+------------ IP    # Interrupt Pending
|||||||||||||||||||+------------- PE    # Paging Enabled
||||||||||||||||||+-------------- IE    # Interrupts Enabled
|||||||||||||||||+--------------- SUP0  # Supervisor Mode 0
||||||||||||||||+---------------- SUP1  # Supervisor Mode 1
|||||||||||||||+----------------- AUX0  # Auxiliary Data 0
||||||||||||||+------------------ AUX1  # Auxiliary Data 1
|||||||||||||+------------------- AUX2  # Auxiliary Data 2
||||||||||||+-------------------- AUX3  # Auxiliary Data 3
|||||||||||+--------------------- AUX4  # Auxiliary Data 4
||||||||||+---------------------- AUX5  # Auxiliary Data 5
|||||||||+----------------------- AUX6  # Auxiliary Data 6
||||||||+------------------------ AUX7  # Auxiliary Data 7
|||||||+------------------------- AUX8  # Auxiliary Data 8
||||||+-------------------------- AUX9  # Auxiliary Data 9
|||||+--------------------------- AUX10 # Auxiliary Data 10
||||+---------------------------- AUX11 # Auxiliary Data 11
|||+----------------------------- AUX12 # Auxiliary Data 12
||+------------------------------ AUX13 # Auxiliary Data 13
|+------------------------------- AUX14 # Auxiliary Data 14
+-------------------------------- AUX15 # Auxiliary Data 15

WORD SIZE
---------

11    8 BIT WORD
01    N/A
10    16 BIT WORD
00    32 BIT WORD


TEST / COMPARE
--------------

In order to test/compare without modifying a register, it is possible to use the
"Never" condition which will allow the operation to be performed and the flags will
be affected as if the operation was completed, with the exception that the OUT
bus will not be activated such that there are no modifications committed.

CONDITION
---------

000                   ; Always.
001                   ; Z
011                   ; C
010                   ; S
100                   ; Never
101                   ; *Z
101                   ; *C
111                   ; *S


STATE MACHINE
-------------

The state machine selects which instruction register should provide the operation
for the current machine state.

STATE BITS
----------

3210
||||
|||+- T1
||+-- T2
|+--- INT
+---- RST


CLOCKS
------

The oscillator (OSC) frequency is divided by 2 to provide the CLK and the IN and OUT clocks
that provide the basis for the T cycles, and provides two clock edges per T cycle
from which to stretch the clock in in order to implement 2 potential WAIT cycles
per T state, one for the IN latch phase, and one for the OUT latch phase.

WAIT STATES
-----------

Wait states are asserted by pulling the *WAIT line low.by open collector. When a wait state is
activated the next LOW period of the CLK signal is stretched (remains low) until the release of
the *WAIT line, and is then followed by the next rising edge of TCLK.


RESET
-----

* Initialize the clock chains.
* Select the XI register RESET word which contains an instruction like "MOV R13,#0x0000"
* Reset state is T1 (EXEC).

SUPERVISORY MODE 0
------------------

Supervisory mode is entered by setting the SUP0 flag in the status register.
R13 is mapped to alternate R13 (R13A).
Supervisory mode 0 takes priority over supervisory mode 1 in the event that
both states are active (i.e. FAULT mode).

SUPERVISORY MODE 1
------------------

Supervisory mode is entered by setting the SUP1 flag in the status register.
R6 is mapped to alternate R13 (R13B).

INTERRUPT
---------

* The 'Interrupt Pending' (IP) and 'Interrupts Enabled' (IE) flags are sampled at the rising edge of the INT1 line.
* If the IP flag and IE flags are set at the rising edge of INT1, then:
  * The IE flag is cleared, disabling further interrupts.
  * The VI0,VI2,VI3 bits in the status register describe which priority interrupt line triggered the interrupt.
  * The 'Supervisor Mode 1' (SUP1) flag is set enabling alternate register R13 (R13b).
  * The T1 cycle of INT1 enables the INT1-T1 microcode instruction to be executed (i.e. ld.l (R13)-,R0).
  * The T1 cycle of INT2 enables the INT2-T1 microcode instruction to be executed (i.e. ld.l R0,$0x00FF or so).

FAULT
-----
* If a fault occures during A T1 cycle, the instructino must be restarted after the FAULT condition is cleared.
* A *FAULT is asserted by the MMU and is an indication that there was a page fault.
* A *FAULT may be asserted at any T1 or T2 cycle.
* If the *FAULT occured during a T1 cycle, then the instruction must be restarted.
* Restarting an instruction is accomplished by subtracting 4 from the R13 register prior to resuming.
* When *FAULT is asserted;
  * The SUP0 flag is set, and register R13 is mapped to alternate register R13a.
  * The instruction register R15 is mapped to the FAULT microcode which should stack R0 so the ISR can later count
    the number of entries on the stack in order to determine in which INT state and which T state the fault occured
    so that R0 may be adjusted accordingly when the program resumes normal operation.
* At the rising edge of the next INT1 cycle;
  * The *FAULT line goes inactive.
  * The pending interrupt #7 is processesed in SUP0 mode (SUP0 take priority over default interrupt SUP1 mode).

BRANCHING
---------

There is no true branch instruction. The "br" instruction is really just a "Type 0" with the branch
offset contained in the immediate data, and an 'add' opcode in the ALU field.

The program counter (R0) is addressable as an ordinary register so any instructions can be used to
modify the contents of R0. Simply load or add an offset into R0 in order to branch.

Conditional branches may be accompished by conditionally adding an offset to R0 using a Type 0 format
instruction.

SUBROUTINES
-----------

There is no single call instruction. A call should first stack the return address and then branch.

IMMEDIATE DATA (Type 0) INSTRUCTION
-----------------------------------

Immediate data is 16 bits wide, and is sign extended to 32 bits.
Immediate data is applied to INb bus. Where the INa and OUT buses
are addressed to the same register.

EXAMPLES:
---------

Many common instructions can be synthisized using macros, for example, there
is no real branch instruction, however you man apply any math or logic to the
R13 (program counter) register as you can any other register. Using this, you
may for convinience sake crate macros to synthesize such instructions.

; Branch (br) macro
br         .macro     %1,%2
           add        %1,$-%2          ; Calculate the target offset and add to destination
           .endmacro
; Branch (br.nz) macro
br.nz      .macro     %1,%2
           add.nz     %1,$-%2          ; Calculate the target offset and add to destination
           .endmacro
; Return (ret) macro                   ; Return from a function that was called with the 'call' macro
ret        .macro
           mov        r0,+(r13)        ; Load r13 from the return address plus offset and increment the stack pointer.
           .endmacro
; push macro
push       .macro     %1
           mov        (r13)-,%1        ; Store the operand on the stack and decrement stack.
           .endmacro
; pop macro
pop        .macro     %1
           mov        %1,+(r13)        ; Increment the stack pointer and fetch the operand from the stack.
           .endmacro
; call macro
call       .macro     %1               ; Function call.
           add        (r13)-,r0,r0,#4  ; Stack the program counter with return offset.
           add        r0,$+target      ; Effect a branch.
           .endmacro

; String copy, dst=(r1), src=(r2)
; Return the dst in r1.
; Use an intermediate register (r3) to facilitate the transfers
; since we have to examine each byte, we can still use the more
; efficient auto increment on the source and destinations pointers
; rather than using two separate increment instructions.
strcpy:    push       r1           ; perserve r0 on the stack
.cp1:      mov.b      r3,(r2)+     ; transfer a byte....
           mov.b      (r1)+,r3     ; ...through R3.
           cp.b       r3,#0        ; done?
           br.nz      r0,.cp1      ; no.
           pop        r1           ; restore r0
           ret                     ; return
		
Watch BRISC/1 ALU Circuit Board being Routed. Like watching paint dry.



Watch BRISC/1 REGISTERS/8 Circuit Board being Routed.